電機工程學系
Permanent URI for this communityhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/85
歷史沿革
本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。
本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。
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Item 24 GHz CMOS 收發器線性化技術(行政院國家科學委員會, 2009-07-31) 蔡政翰本計畫將開發應用於下一代寬頻高速的無線通信系統的24GHz 高線性度收發器積 體電路，實現的方法將使用互補式金氧半導體之積體電路技術。計畫目標是研究利用矽 基製程技術，開發24GHz 收發器積體電路，包括功率放大器、低雜訊放大器、與混頻 器等。並且爲了滿足現今高速無線數位通信系統嚴格的線性度要求，本計畫針對發射器 中的關鍵元件，作線性度的分析，並且發展線性化技術，達到在有限的電能消耗下，設 計一24GHz CMOS 高線性度收發器的目標。Item A 30-60GHz CMOS sub-harmonic IQ de/modulator for high data-rate communication system applications(2009-01-22) Wei-Heng Lin; Wei-Lun Chang; Jeng-Han Tsai; Tian-Wei HuangA 30-60 GHz sub-harmonic IQ de/modulator using TSMC CMOS 0.13-mum process is presented in this paper. The IQ de/modulator consists of two FET resistive mixers, a 90deg coupler, and a Wilkinson power divider. The resistive mixer could simultaneously used as a up-converted or a down-converted mixer. Therefore, the measurement of the FET resistive mixer based modulator or demodulator will be done. The die size is 0.78 mm times 0.58 mm. Both IQ demodulator and modulator feature the conversion loss of -16plusmn1 dB and good demodulation and modulation capacity.Item A 50-to-62GHz wide-locking-range CMOS injection-locked frequency divider with transformer feedback(2008-06-17) Yu-Hang Wong; Wei-Heng Lin; Jeng-Han Tsai; Tian-Wei HuangA 50-to-62 GHz injection-locked frequency divider (ILFD) with transformer feedback technique is designed in 0.13-mum CMOS technology for wide locking range. The measurement results show that the free-running frequency is 55.3 GHz and the total locking range is 12 GHz (>20%) at the input power level of 0 dBm while consuming 10.8 mW from a 0.9 V power supply. The phase noise of the divider is -124.93 dBc/Hz at 1 MHz offset from the carrier. This wide locking range ILFD is suitable for integration into a phase-lock-loop (PLL) system because of its small size and no need of extra control signal.Item A V-band fully-integrated CMOS distributed active transformer power amplifier for 802.15.TG3c wireless personal area network applications(2008-10-15) Yung-Nien Jen; Jeng-Han Tsai; Tian-Wei Huang; Huei WangA 60-GHz fully-integrated and broadband distributed active transformer (DAT) power amplifier (PA) is implemented in 90-nm CMOS technology. The PA performs a flat small signal gain of 26 plusmn 1 dB from 57 to 69 GHz which covers full band for 60-GHz wireless personal network (WPAN) applications. By using the DAT output combine structure, this PA delivers 18-dBm measured output power with 12.2% PAE at 60 GHz with a compact chip size. To the best of our knowledge, this DAT CMOS PA demonstrates the highest output power among the reported 60-GHz CMOS PAs to date.Item A 90-nm CMOS broadband and miniature Q-band balanced medium power amplifier(2007-06-08) Jeng-Han Tsai; Yi-Lin Lee; Tian-Wei Huang; Cheng-Ming Yu; John G. J. ChernThis paper presents a Q-band balanced medium power amplifier fabricated using standard 90-nm 1P9M CMOS technology. The balanced amplifier, which is constructed with two broadband amplifiers and two broadside couplers using thin-film microstrip (TFMS) line technique, has a compact chip size of 0.78 x 0.92 mm2. The MMIC demonstrates a measured gain of 14.5 dB at 48 GHz. With the feature of the balanced amplifier, the MMIC has a 3-dB bandwidth up to 37.2 % from 35 to 51 GHz with flat gain and return loss frequency response. Furthermore, the balanced amplifier delivers a saturation output power of 10.6 dBm with 8% PAE and OPldB is 7.5 dBm.Item A 68-83-GHz power amplifier in 90 nm standard CMOS(2009-06-12) Jeffrey Lee; Chung-Chun Chen; Jeng-Han Tsai; Kun-You Lin; Huei WangA balanced PA covering 68-83 GHz is developed in 90 nm CMOS. Using wideband power matching topology, the PA achieves power gain of greater than 18.1 dB from 68 to 83 GHz and gain flatness within 0.2 dB from 68 to 78 GHz. The PA has a maximum saturation output power of 14 dBm at 70 GHz, and greater than 11.8 dBm from 68 to 83 GHz. The best P1dB is 12 dBm at 68 GHz, and greater than 8.3 dBm from 68 to 83 GHz.Item A 25-75-GHz broadband Gilbert-cell mixer using 90-nm CMOS technology(IEEE Microwave Theory and Techniques Society, 2007-04-01) Jeng-Han Tsai; Pei-Si Wu; Chin-Shen Lin; Tian-Wei Huang; John G.J. Chern; Wen-Chu Huang; Huei WangA compact and broadband 25-75-GHz fully integrated double-balance Gilbert-cell mixer using 90-nm standard mixed-signal/radio frequency (RF) CMOS technology is presented in this letter. A broadband matching network, LC ladder, for Gilbert-cell mixer transconductance stage design is introduced to achieve the flatness of conversion gain and good RF port impedance match over broad bandwidth. This Gilbert-cell mixer exhibits 3plusmn2dB measured conversion gain (to 50-Omega load) from 25 to 75GHz with a compact chip size of 0.30mm2. The OP1 dB of the mixer is 1dBm and -4dBm at 40 and 60GHz, respectively. To the best of our knowledge, this monolithic microwave integrated circuit is the highest frequency CMOS Gilbert-cell mixer to dateItem A 30-100-GHz wideband sub-harmonic active mixer in 90-nm CMOS technology(IEEE Microwave Theory and Techniques Society, 2008-08-01) Jeng-Han Tsai; Hong-Yuan Yang; Tian-Wei Huang; Huei WangThis letter presents a 30-100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits -1.5 plusmn 1.5 dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm2. The OP1 dB of the mixer is -10.4 dBm and -9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.Item A 86- to 108-GHz Amplifier in 90-nm CMOS(IEEE Microwave Theory and Techniques Society, 2008-02-01) Yu-Sian Jiang; Zuo-Min Tsai; Jeng-Han Tsai; Hsien-Te Chen; Huei WangThis letter presents a CMOS amplifier with 22 GHz 3-dB bandwidth ranging from 86 to 108 GHz. The amplifier is implemented in 90 nm mixed signal/radio frequency (RF) CMOS process using three-stage cascode RF NMOS configuration. It achieves a peak gain of 17.4 dB at 91 GHz from the measured results. To our knowledge, this is the highest frequency CMOS amplifier reported to date.Item A W-band medium power amplifier in 90 nm CMOS(IEEE Microwave Theory and Techniques Society, 2008-12-01) Yu-Sian Jiang; Jeng-Han Tsai; Huei WangA W-band CMOS medium power amplifier (PA) is presented in this letter. The circuit is implemented in 90 nm mixed signal/radio frequency CMOS process. By utilizing balanced architecture, the PA demonstrated a measured maximum small signal gain of 17 dB with 3 dB bandwidth from 91 to 108 GHz. The saturation output power (P sat) is 12 dBm between 90 and 100 GHz for V ds of each transistor at 1.5 V. To our knowledge, this is the highest frequency CMOS PA to date.