電機工程學系
Permanent URI for this communityhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/85
歷史沿革
本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。
本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。
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Item CMOS oversampling ΔΣ magnetic-to-digital converters(IEEE Solid-State Circuits Society, 2001-10-01) Chien-Hung Kuo; Shr-Lung Chen; Lee-An Ho; Shen-Iuan LiuIn this paper, two CMOS oversampling delta-sigma (ΔΣ) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) ΔΣ modulator. The second one directly uses the MOP to realize a first-order SC ΔΣ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-μm CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least ±100 mT. The gain errors within ±100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 μT for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectivelyItem A double-sampling pseudo-two-path bandpass ΔΣ modulator(Institute of Electrical and Electronics Engineers�(IEEE), 2000-02-01) Shen-Iuan Liu; Chien-Hung Kuo; Ruey-Yuan Tsai; Jingshown WuA double-sampling pseudo-two-path bandpass modulator is proposed. This modulator has an output rate equal to twice the clock rate, uses 2 operational amplifiers (op-amps) for an th-order noise transfer function, and has reduced clock feedthrough in the signal path band. The required clocks can be simpler to implement than the conventional pseudo-two-path techniques. The measured signal-to-noise ratio and dynamic range of the fourth-order double-sampling pseudo-two-path bandpass modulator in a 30-kHz bandwidth at a center frequency of 2.5 MHz (at a clock frequency of 5 MHz) are 62 and 68 dB, respectively.Item A Sub-1V Fourth-Bandpass Delta-Sigma Modulator(Springer Verlag (Germany), 2003-12-01) Hsiang-Hui Chang; Chien-Hung Kuo; Ming-Huang Liu; Shen-Iuan LiuA sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using voltage multipliers or bootstrapping switches. A two-path structure is applied to relax the settling requirement. Implemented in a 0.25-μm one-poly, five-metal standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 58.2 db and a dynamic range (DR) of 64 db in a 60 KHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm2.Item A 1-V 10.7MHz Fourth-Order Bandpass ΔΣ Modulators Using Two Switched Opamps(Institute of Electrical and Electronics Engineers�(IEEE), 2004-11-01) Chien-Hung Kuo; Shen-Iuan LiuA 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25- m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is 65 dBc below the desired signal.Item Magnetic-to-Digital Converters Using Single-Amplifier-Based Second-Order Delta-Sigma Modulators(Institute of Electrical and Electronics Engineers (IEEE), 2004-04-01) Chien-Hung Kuo; Shr-Lung Chen; Shen-Iuan LiuIn this paper, two magnetic-to-digital converters (MDCs) using single-amplifier-based second-order delta–sigma modulators (DSMs) are presented to detect the dc magnetic field. The proposed second-order DSM required only a single-operational amplifier to achieve the second-order noise shaping. Both the proposed circuits have been fabricated in a 0.5- m CMOS DPDM process, and the resolution of 11 bits can be achieved. The measured sensitivities are 1.486 and 0.459 mV/mT, and the minimum detectable magnetic fields are 0.6 mT and 0.4 mT for the MDC with and without the pre-amplifier, respectively. Both the measured nonlinearities are smaller than 1.3% within the range of 100 mT.Item Multi-bit Delta-Sigma Modulator Using a Modified DWA Algorithm(Springer Verlag (Germany), 2002-12-01) Chien-Hung Kuo; Tzu-Chien Hsueh; Shen-Iuan LiuA four pointer data weighted averaging (FPDWA) algorithm is presented to reduce the nonlinearity of the feedback multi-bit digital-to-analog converter (DAC) for delta-sigma modulators. By utilizing the proposed algorithm, the noise power caused by element mismatch can be reduced. A nine-level second-order delta-sigma modulator has been implemented in a double-poly double-metal 0.35 μm CMOS process. Experimental results indicate the peak SNDR reaches 86.59 dB within bandwidth of 22 kHz. The maximum input amplitude is −7 dB below the full scale with 10-kHz input frequency, the sampling frequency is 5 MHz, and the OSR is around 113. The power consumption is 6.27 mW for a power supply of 3.3 V.Item CMOS Magnetic Field to Frequency Converter(Institute of Electrical and Electronics Engineers�(IEEE), 2003-04-01) Shr-Lung Chen; Chien-Hung Kuo; Shen-Iuan LiuIn this paper, a CMOS magnetic field to frequency converter with high resolution is presented. It is composed of two voltage-controlled ring oscillators whose output frequency differences linearly vary with the magnetic field perpendicular to the chip surface. The prototype circuit has been fabricated in a 0.5- m CMOS process and operated at a 5-V supply voltage. The measured sensitivity is 24 kHz/mT and the power consumption is 5.1 mW. The small equivalent resolution of at least 20 T can be achieved. The frequency offset is 42 kHz when no magnetic field applied. Its nonlinearity within 120 mT is smaller than 0.56%.Item A magnetic field to digital converter using PWM and TDC techniques(IET, 2006-06-01) Chien-Hung Kuo; Shr-Lung Chen; Shen-Iuan LiuA high resolution magnetic-field-to-digital converter (MDC) is presented. It is composed of a magnetic-field-to-pulse width converter (MPC), a cyclic pulse-shrinking time-to-digital converter (TDC) and a polarity detector. This prototype circuit has been fabricated in a 0.5mm CMOS DPDM process. With a clock rate of 16.6 kHz, the power consumption is 42.5 mW under 5 V supply voltage. The equivalent resolution less than 16mT can be achieved within the range of 710 mT. After off-line calibration, the remaining offset is 0.017 mT and its gain error is smaller than 0.4%.