先進矽鍺元件之應力估算與效能分析

Abstract

隨電子產品輕薄短小及功能多樣化之潮流，傳統之矽基半導體元件已無法符合下一世代元件於速度或功能之要求，因此除藉由縮減元件特徵尺寸外，應變工程之導入對於奈微電子元件之效能提升益顯重要。然而，電路圖案化之影響諸如具突起之多晶矽閘極對窄通道元件之引致應力大小，相關文獻卻鮮少有完整地討論。 有鑑於此，本研究系統性地探討應變工程對於突出之多晶矽閘極寬度於具窄通道之P型半導體元件之性能表現。本論文分為兩部份，首先使用因子實驗設計概念結合有限元素之模擬法，對PMOS半導體元件進行應力模擬。分析時選擇四個重要設計因子，分別為延伸閘極寬度、源∕汲極長度、元件通道寬度，以及CESL內含應力值進行變異數分析，並討論其對於載子遷移率之影響性。由變異數分析可得知其因子重要影響程度前三項依序為CESL之應力值、CESL應力值與延伸閘極寬度兩因子間之交互作用，延伸閘極寬度。由上述分析獲知，延伸閘極寬度這一設計因子對於半導體元件其載子遷移率增益之影響為十分重要。其次，為了瞭解CESL應力與延伸閘極寬度兩因子間之交互作用關係，故於本研究使用中央合成設計法得到該因子間之反應曲面圖。藉由該曲面圖吾人可以進而獲得其優化之組合關係。 第二部份，由於在文獻中可得知矽鍺合金源/汲極長度愈長則P型半導體元件其阻值會隨之減少。因此對不同大小之延伸閘極寬度與矽鍺合金之源/汲極長度進行敏感度分析，討論元件不同方向其應力值與載子遷移率之增益。分析結果指出當延伸閘極寬度於0.2 m時，其所貢獻之載子遷移率為最大。

With the trend of multi-function and minimizing volume, traditional silicon-based semiconductor transistors have not met the performance requirements of next-generation devices. Consequently, in addition to diminish the characteristic sizes of nano-scale transistors, an introduction of advanced strained engineering is significant to enhance their performances. However, effects of pattern layouts such as different width of extended poly gate on narrow channel width on P-type metal oxide semiconductor field (PMOSFETs) has little reported as well as discussed completely. For this reason, this investigation analyzes PMOSFETs with a combination of a narrow gate length and extended poly width by using three dimensional finite element simulations integrated with the concept of factorial design of experiments. In the first part of this thesis, four design factors, including extended poly width, source/drain length, gate length, and the magnitude of CESL stressor, are selected to perform the analysis of variance (ANOVA) to confirm the interpretation and significance of effects for mobility gain of devices. The ANOVA results indicate that the effect importance is CESL stressor, interaction between CESL stressor and extended poly gate width, and extend poly gate width in sequence. From the above-mentioned results, it is found that extended poly width plays an important role for the mobility enhancement of devices. Moreover, for the purpose of investigating the interaction between CESL stressor and extended poly gate width, the central composite design is utilized to construct the contour of response surface. Subsequently, the better combinations of the factors are suggested in this thesis. In the second part, the sensitive analysis of stress effects within Si channel and corresponding mobility gains under the considerations of extended poly gate width and silicon germanium alloy embedded in the source/drain (S/D) region is implemented. The results point out that the mobility gain is maximum as the extended poly width is equal to 0.2 m.