氧化鋅奈米線陣列披覆PVDF製作可撓性壓電元件之輸出電壓特性研究

Abstract

本研究先利用濺鍍機在可撓式銅基板上沉積一層氧化鋅種子層，再將沉積種子層過後的銅基板經過水熱法長出一維結構之氧化鋅奈米線，透過不同氧化鋅種子層的粗糙度改變氧化鋅奈米線之線徑與線長：氧化鋅種子層粗糙度低，奈米線長且細，但容易造成奈米線叢聚現象；氧化鋅種子層粗糙度高製備出奈米線線徑粗，因線徑粗使奈米線叢聚現象降低。因製備完成氧化鋅奈米線後，需將PVDF薄膜旋塗於氧化鋅奈米線上，若奈米線有叢聚現象，PVDF溶液較不易均勻沉浸於奈米線中。接下來探討PVDF在何種結晶的環境下和厚度，能有效的提高PVDF的壓電輸出特性，一般PVDF的熔點溫度在160℃。研究成果指出，PVDF薄膜在300 rpm的轉速有最大的壓電輸出，且在烘烤時間50分鐘也能有效的使壓電輸出達到最佳化。 雖然氧化鋅奈米線本身也是壓電材料，但其壓電輸出特性卻非常小；而在PVDF薄膜上，雖材料本身耐強度與高壓電輸出特性，但其壓阻高所造成的靈敏性低之缺點，故在最後研究，將結合兩種材料以達到相輔相成的效用在，所以近一步探討PVDF薄膜在有無披覆氧化鋅奈米線時的壓電輸出特性的差異，結果顯示披覆氧化鋅奈米線時之壓電輸出特性增加、反應時間減少，都是因氧化鋅奈米線高體表面積的優點，使PVDF薄膜能突破本身低靈敏性的特性，能有潛力成為高敏性與高輸出之可撓式攜帶電子元件。Herein this study reports the preparation of ZnO nanowires by using the hydrothermal method. Different lengths and width of ZnO nanowires array can be obtained by changing the sputtering parameter. We can obtain the longer and thick of ZnO nanowires with low surface roughness, but this result may bundle the nanowires. So we increase the surface roughness to avoid bundling the nanowires. PVDF was dissolved in acetone. The solution was dropped onto the substrate containing the ZnO nanostructures. Following spin-coating at 300, 500, 700, and 1000 rpm for 60 s, the film was poled at 160℃ for 30, 40, and 50 min. We can get the best output piezoelectric property from PVDF at 300 rpm and 50 min. To compare the pressure and bending sensing properties of the PVDF and PVDF/ZnO composite film. As the result, the PVDF/ZnO nanowires composite film exhibited the greatest signal in response, especially for a micro-loading sensing. Because of the 1D vertically ZnO nanowires, they generate an enhanced piezoelectric response to increase the sensitivity and lower the contact resistance at PVDF/Cu interface. In order o increase the output piezoelectric property, we increase the sensing area. The dipole moment under different sensing area determines the proportionally increased output voltage.