Layer Assignment for Multi-layer PCB and VLSI Routing

dc.contributor國立臺灣師範大學資訊教育研究所zh_tw
dc.contributor.author張國恩zh_tw
dc.contributor.author方松川zh_tw
dc.date.accessioned2014-10-30T09:32:07Z
dc.date.available2014-10-30T09:32:07Z
dc.date.issued1991-07-01zh_TW
dc.description.abstractVLSI佈線中的佈局層指定問題是決定佈局中各線段所應處的佈局層,使得所產生的穿孔數最少。本文中,首先將多層佈局層指定問題轉換成圖形的縮減問題,然後按照所建的圖形縮減模式設計出一種啟發式的演算法以解決此問題。本演算法完成後使用著名的佈線例子以評估之。評估結果知大約有百分之 38.5 的穿孔被減少了。zh_tw
dc.description.abstractThe layer assignment problem for VLSI routing is the problem of determining which layers can be used for routing the wire segments in the interconnections of nets so that the number of vias is minimized. In this paper, we first transform the problem of layer assignment for multi-layer routing to the graph contractability problem and then a heuristic algorithm is proposed on the basis of the graph contractability model. The algorithm was evaluated using Deustch's five-layer difficult example. The result showed that the number of vias is reduced 38.5 percent.en_US
dc.identifierntnulib_tp_A0904_01_009zh_TW
dc.identifier.issn0253-3839zh_TW
dc.identifier.urihttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/34310
dc.languageenzh_TW
dc.publisher中國工程師學會zh_tw
dc.relation中國工程學刊,14(4),373-382。zh_tw
dc.relationJournal of the Chinese Institute of Engineers (JCIE), 14(4), 373-382.en_US
dc.subject.other佈局層指定zh_tw
dc.titleLayer Assignment for Multi-layer PCB and VLSI Routingen_US

Files

Collections