整合氧化鋁鐵電記憶體之氧化錫薄膜電晶體元件電性探討之研究

Abstract

本研究首先探討鐵電電容在不同退火溫度下之影響。鐵電電容在600oC~800oC中，漏電流隨著退火溫度上升而無明顯變化，有利於不同溫度下之製程整合，而在鐵電特性上，會隨著溫度上升而增強，但同時極化迴圈開口也會增大。在P型薄膜電晶體中，Id-Vd輸出特性有明顯截止區與飽和區，在汲極電壓與閘極電壓為-2V時，電流為1.10A。Id-Vg轉移特性中，在±2.5V中有3個數量級之開關電流比 。漏電流約在10-9 A，顯示10nm之氧化鋁鉿薄膜較好的閘極介電薄膜。 在串聯HfAlOX薄膜厚度為10nm之鐵電電容中，電容面積隨著200x200m2至50x50m2，Current-Ratio Memory Window從67.00增加至362.80。當電容越小，匹配越好，Current-Ratio Memory Window越大。在相同面積50x50m2下改變不同串聯厚度，從5nm至10nm，Current-Ratio Memory Window從7.11增加至362.80，當厚度越厚，匹配越好，Current-Ratio Memory Window越大。根據參考文獻之模擬，當電晶體電容與鐵電電容在電荷(Q)-電容(C)圖中相交於兩點，電壓來回掃時，會分別經過這兩點，而使電荷陡峭上升，因而形成電滯迴圈，在固定電晶體電容值，改變鐵電電容值時，鐵電電容越小則Current-Ratio Memory Window越大，實驗結果與參考文獻相符。在資料儲存Retention測試中，P型氧化錫薄膜電晶體串聯厚度為10nm、面積50x50m2氧化鋁鉿鐵電電容經過1000秒後有最高的開關電流比，為較佳測試條件。

Abstract This research explored the effects of ferroelectric capacitors at different annealing temperatures at first. In the 600oC, 700oC, and 800oC ferroelectric capacitors, the leakage current does not fluctuate significantly with the increase of the annealing temperature, which is beneficial to the process integration at different temperatures. The ferroelectric characteristics will increase with the temperature rise, but at the same time Pr will also rise. In the P-type thin film transistor, there are obvious cut-off regions and saturation regions in the Id-Vd characteristics. The drain current is 1.10A when the gate and the drain voltage are -2V. In the Id-Vg characteristics, there are three order on/off ratios in ±2.5V. The leakage current is about 10-9A, showing a high deposition quality of the 10 nm HfO2 film. In the 10 nm HfAlOX ferroelectric layer in series with P-type TFT, as the capacitance area increases from 200x200m2 to 50x50m2, the Current-Ratio Memory Window increases from 67.00 to 362.80. When the capacitance is smaller, the better the matching, the larger the Current-Ratio Memory Window. When the different thickness of ferroelectric capacitors is changed in the area of 50x50m2, from 5nm to 10nm, the memory window increases from 7.11 to 362.80. When the thickness is thicker, the better the matching, the larger the memory window. According to the simulation of the reference, when the transistor capacitance and the ferroelectric capacitance intersect at two points in the charge (Q)-capacitance (C) diagram, the charge will rise steeply. It leads to the hysteresis window formed. When the value of the transistor capacitance is fixed, the smaller the ferroelectric capacitance is, the larger the memory window is. The reference literature supports the experimental results. In the data storage Retention test, the ferroelectric capacitance whose thickness is 10 nm and the area is 50x50m2 has the highest Ion/Ioff ratio after 1000 seconds, which is a better test condition.