電機工程學系

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歷史沿革

本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。

本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。

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Subject: search.filters.subject.Linearizer

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    28GHz砷化鎵增強型pHEMT功率放大器與PIN二極體切換器設計
    (2021) 謝雲岳; Hsieh, Yun-Yueh
    第一顆電路為內具線性器之28 GHz二級功率放大器，透過傳輸線匹配網路達成輸出功率阻抗匹配、輸入共軛匹配之效果。當VG = 0.5 V時，且線性器為關閉狀態(Vctrl = 0 V)時，在頻率為28 GHz下，其功率增益(Power gain)約為21.16 dB，飽和輸出功率Psat約為24.63 dBm，1-dB增益壓縮點之輸出功率(OP1dB)約為24.01 dBm，最大功率附加效率Peak PAE約為36.41 %，而當線性器為開啟狀態((Vctrl1 = 0.35 V、Vctrl2 = 0.15 V)且頻率為28 GHz時，IMD3在-40 dBc時的輸出功率為16 dBm，整體晶片佈局面積為1 mm × 2 mm。第二顆電路為28 GHz PIN二極體切換器，採用四分之一波長線的SPDT架構。當操作頻率為28 GHz且VON為-4 V、VOFF為1.3 V時， 插入損耗約為2.15 dB，輸入輸出反射損耗(S11、S22)分別為14.07 dB與9.92 dB，0.1-dB增益壓縮點之輸入功率(IP0.1dB)約為17 dBm，整體晶片佈局面積為1 mm × 1 mm。
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    Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers
    (IEEE Microwave Theory and Techniques Society, 2006-06-01) Jeng-Han Tsai; Hong-Yeh Chang; Pei-Si Wu; Yi-Lin. Lee; Tian-Wei Huang; Huei Wang
    A 44-GHz monolithic microwave integrated circuit (MMIC) low-loss built-in linearizer using a shunt cold-mode high-electron mobility transistor (HEMT), based on the predistortion techniques, is presented in this paper. The proposed cold-mode HEMT linearizer can enhance the linearity of the power amplifier (PA) with a low insertion loss (IL<2 dB), a compact die-size, and no additional dc power consumption. These advantages make the linearizer more suitable for millimeter-wave (MMW) applications. The physical mechanism of the gain expansion characteristics of the proposed linearizer is analyzed. A systematic design procedure for a low-loss linearizer is developed, which includes: 1) insertion loss minimization through a device-size selection and 2) linearity optimization through a two-tone test. To demonstrate the general usefulness of the proposed linearizer, the linearizer was applied to a two-stage 44-GHz MMIC medium PA and a commercial MMW PA module. After linearization, the output spectrum regrowth is suppressed by 7-9 dB. To keep the adjacent channel power ratio below -40 dBc, the output power has been doubled from 15 to 18 dBm at 44 GHz. The error vector magnitude of the 16-quadrature amplitude modulation signal can be reduced from 6.11% to 3.87% after linearization. To the best of our knowledge, this is the first multistage MMW PA with a low-loss built-in linearizer