電機工程學系

Permanent URI for this communityhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/85

歷史沿革

本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。

本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。

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    Design of 1.2 V broadband, high data-rate CMOS MMW I/Q modulator and demodulator using modified Gilbert-cell mixer
    (IEEE Microwave Theory and Techniques Society, 2011-05-01) Jeng-Han Tsai
    In this paper, low-voltage evolution and high-speed operation mixer design are presented for millimeter-wave (MMW) CMOS in-phase/quadrature (I/Q) modulator and demodulator. The modified Gilbert-cell mixer architecture, which eliminates the three-level transistors stacking in the conventional Gilbert-cell mixer, can operate at a reduced supply voltage while maintaining reasonable performance. In addition, IF transimpedance amplifier buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW gigabit wireless transmission link applications. Using a 0.13-μm CMOS process, the I/Q modulator and demodulator formed with the modified Gilbert-cell mixers are demonstrated at the MMW. Under 1.2-V standard supply voltage, the modulator and demodulator exhibit excellent conversion gain (CG) flatness of -3.5 ±1.5 dB and -3 ±1.5 dB from 41 to 69.5 GHz and 31 to 69 GHz, respectively. For 60-GHz wireless personal area network applications, π/4 differential quadrature phase-shift keying, 16 quadrature amplitude modulation, and binary phase-shift keying modulation signal tests are successfully performed through the direct-conversion system. The results show that the presented monolithic microwave integrated circuits can operate at low-voltage and low-power while providing good CG and high data rate, even up to multigigabit.
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    A 60-GHz CMOS power amplifier with built-in pre-distortion linearizer
    (Institute of Electrical and Electronics Engineers (IEEE), 2011-12-01) Jeng-Han Tsai; Chung-Han Wu; Hong-Yuan Yang; Tian-Wei Huang
    A built-in pre-distortion linearizer using cold-mode MOSFET with forward body bias is presented for 60 GHz CMOS PA linearization on 90 nm CMOS LP process. The power ampli- fier (PA) achieves a of 10.72 dBm and of 7.3 dBm from 1.2 V supply. After linearization, the has been doubled from 7.3 to 10.2 dBm and the operating PAE at consequently improves from 5.4% to 10.8%. The optimum improvement of the IMD3 is 25 dB.