電機工程學系

Permanent URI for this communityhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/85

歷史沿革

本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。

本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。

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系所網址：https://www.ee.ntnu.edu.tw/

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Author: search.filters.author.Kuan-Yi Lee

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    使用AB類/AB類開關運算放大器技術之0.7伏低功率低失真多位元三角積分調變器
    (2010) 李冠毅; Kuan-Yi Lee
    　　積體電路隨著製程技術的進步，已進入奈米的世界。然而在類比電路的設計與實現上卻沒有明顯受益，肇因於臨界電壓並未顯著減少，這對類比電路的設計是一大考驗。特別是低電壓電路要維持與一般電壓相同之效能是一項很大的挑戰。三角積分調變器對於類比電路元件的非理想特性不敏感，常運用於高解析度之電路，再結合超取樣技術、切換式運算放大器技術及雙取樣技術，可提升電路的性能。 　　本論文提出在供應電壓為0.7V的操作下，適用於音頻範圍之三階多位元低通三角積分調變器，使用TSMC標準0.18微米製程下完成兩個電路，一為改良型三階低失真三角積分調變器，另一個為具數位加強的三階低失真三角積分調變器。操作於25 KHz的頻寬，取樣頻率為4 MHz，個別的最大SNDR各為79.94 dB和80.14 dB，功率消耗為0.8897 mW和0.566 mW。
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    A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications
    (2008-12-03) Chien-Hung Kuo; Kuan-Yi Lee; Shuo-Chau Chen
    In this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.
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    An Ultra Low-Power Delta-Sigma Modulator Using Charge-Transfer Amplifier Technique
    (2008-12-03) Chien-Hung Kuo; Kuan-Yi Lee; Ming-Feng Wu
    In this paper, an ultra low-power delta-sigma (DeltaSigma) modulator applying charge-transfer amplifier (CTA) technique for voice-band applications is presented. Both the fully-differential charge-transfer amplifier and integrator are developed for higher dynamic range of the modulator. A 67 dB of the peak SNR within a 4 kHz of bandwidth is reached in the presented modulator under a 2.5 MHz of sampling rate. The prototype circuit has been implemented in a 0.18 mum 1P6M CMOS technology. The chip area excluding PADs is 0.50 times 0.28 mm2. Due to its zero static current of CTA, only dynamic power is consumed in the circuit. The power consumption of the analog part of the presented second-order DeltaSigma modulator is only 3.4 muW. The total power consumption of the whole modulator is 36 muW at a 1.8 V of supply voltage.