電機工程學系
Permanent URI for this communityhttp://rportal.lib.ntnu.edu.tw/handle/20.500.12235/85
歷史沿革
本系成立宗旨在整合電子、電機、資訊、控制等多學門之工程技術，以培養跨領域具系統整合能力之電機電子科技人才為目標，同時配合產業界需求、支援國家重點科技發展，以「系統晶片」、「多媒體與通訊」、與「智慧型控制與機器人」等三大領域為核心發展方向，期望藉由學術創新引領產業發展，全力培養能直接投入電機電子產業之高級技術人才，厚植本國科技產業之競爭實力。
本系肇始於民國92年籌設之「應用電子科技研究所」，經一年籌劃，於民國93年8月正式成立，開始招收碩士班研究生，以培養具備理論、實務能力之高階電機電子科技人才為目標。民國96年8月「應用電子科技學系」成立，招收學士班學生，同時間，系所合一為「應用電子科技學系」。民國103年8月更名為「電機工程學系」，民國107年電機工程學系博士班成立，完備從大學部到博士班之學制規模，進一步擴展與深化本系的教學與研究能量。
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Item A 0.8V SOP-Based Cascade Multibit Delta-Sigma Modulator for Wideband Applications(2008-12-03) Chien-Hung Kuo; Kuan-Yi Lee; Shuo-Chau ChenIn this paper, a 0.8 V switched-opamp (SOP)-based 2-2 cascade delta-sigma modulator for wideband applications is presented. The first stage uses low-distortion topology to release the requirement of SOP due to only the quantization noise in integrator path. The second stage employs a CIFB structure without the use of summer in front of the quantizer to decrease the power consumption. Double sampling technique combined with the SOP with two output stages is used to promote the clock efficiency. The proposed fourth-order DeltaSigma modulator with CIFFCIFB structure has been implemented in a 0.13 mum CMOS 1P8M technology. The core area excluding PADs is 1.66times1.62 mm2. The peak signal-to-noise plus distortion ratio (SNDR) and dynamic range (DR) of the presented modulator within a 1.1 MHz of bandwidth are 77.9 dB and 85 dB, respectively, under a 20 MHz of clock rate. The power dissipation of the presented DeltaSigma modulator is 15.7 mW at a 0.8 V of supply voltage.Item A Sixth-Order 4-2 SMASH CIFF Complex Bandpass Delta-Sigma Modulator with Delaying Digital Input Feedforward(2010-06-02) Chien-Hung Kuo; Hung-Jing Lai; Deng-Yao ShiIn this paper, a sixth-order sturdy multi-stage noise shaping (SMASH) bandpass delta-sigma (ΔΣ) modulator with delaying digital input feedforward (DFF) structure is presented. The second-order ΔΣ modulator with cascade integrators and distributed feedforward (CIFF) is utilized in each stage to reduce the signal swing. Hence, the requirement of opamp and the power consumption of circuits can be reduced due to the suppression of the signal swing and the discarding of the digital cancellation filters. One pair of complex zeros is designed within signal bandwidth to effectively suppress the noise floor of the presented modulator. The sub-sampling technique is adopted to reduce the clock frequency and the requirement of opamp. Simulation results confirm the feasibility of the proposed SMASH CIFF bandpass ΔΣ modulator with delaying DFF structure. The proposed bandpass ΔΣ modulator compared to the single-loop AFF structure, the signal-to-noise plus distortion ratio (SNDR) could be increased by 12 dB, and the dynamic range (DR) could be extended by roughly 15 dB in a 200 kHz of signal bandwidth centered at 10.7 MHz.Item An Ultra Low-Power Delta-Sigma Modulator Using Charge-Transfer Amplifier Technique(2008-12-03) Chien-Hung Kuo; Kuan-Yi Lee; Ming-Feng WuIn this paper, an ultra low-power delta-sigma (DeltaSigma) modulator applying charge-transfer amplifier (CTA) technique for voice-band applications is presented. Both the fully-differential charge-transfer amplifier and integrator are developed for higher dynamic range of the modulator. A 67 dB of the peak SNR within a 4 kHz of bandwidth is reached in the presented modulator under a 2.5 MHz of sampling rate. The prototype circuit has been implemented in a 0.18 mum 1P6M CMOS technology. The chip area excluding PADs is 0.50 times 0.28 mm2. Due to its zero static current of CTA, only dynamic power is consumed in the circuit. The power consumption of the analog part of the presented second-order DeltaSigma modulator is only 3.4 muW. The total power consumption of the whole modulator is 36 muW at a 1.8 V of supply voltage.Item A Third-Order Four-Bit Delta-Sigma Modulator with MCIFF Structure for Wideband Applications(2008-08-20) Chien-Hung Kuo; Chien-Yu ChenThis paper presents a third-order low-distortion multi-bit delta-sigma modulator for wideband applications. The modified cascade integrators with distributed feedforward (MCIFF) structure without summer in front of quantizer is realized to save the power consumption in the presented modulator. The impact of the nonlinearity of opamp on the presented multi-bit MCIFF modulator is discussed. The prototype circuit is realized in the third-order 4-bit ΔΣ modulator, which has been fabricated in 0.18μm 1P6M CMOS process. The simulated signal-to-noise plus distortion ratio (SNDR) of the modulator within a 200 kHz of bandwidth under a 13.76 MHz of clock rate is 100.53 dB. The total power consumption of the modulator is 5.03 mW at a 1.8 V of supply voltage.Item A Multi-Band Delay-Locked LOOP with Fast-Locked and Jitter-Bounded Features(2008-11-05) Chien-Hung Kuo; Meng-Feng Lin; Chien-Hung ChenIn this paper, a multi-band delay-locked loop with fast-locked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLL-based frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 mum 1P6M CMOS process. The core area excluding PADs is 0.34times0.41 mm2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.Item CMOS oversampling ΔΣ magnetic-to-digital converters(IEEE Solid-State Circuits Society, 2001-10-01) Chien-Hung Kuo; Shr-Lung Chen; Lee-An Ho; Shen-Iuan LiuIn this paper, two CMOS oversampling delta-sigma (ΔΣ) magnetic-to-digital converters (MDCs) are proposed. The first MDC consists of the magnetic operational amplifier (MOP) and a first-order switched-capacitor (SC) ΔΣ modulator. The second one directly uses the MOP to realize a first-order SC ΔΣ modulator. They can convert the external magnetic field into digital form. Both circuits were fabricated in a 0.5-μm CMOS double-poly double-metal (DPDM) process and operated at a 5-V supply voltage and the nominal sampling rate of 2.5 MHz. The dynamic ranges of these converters are at least ±100 mT. The gain errors within ±100 mT are less than 3% and the minimum detectable magnetic field can reach as small as 1 mT. The resolutions are 100 μT for both of the two MDCs. The measured sensitivities are 1.327 mv/mT and 0.45 mv/mT for the first and the second MDC, respectivelyItem A Low-Power High-Gain Rail-to-Rail Input/Output Operational Amplifier(2007-08-01) Chien-Hung Kuo; Hwa-Ming Lu; Wei-Hsien FangItem A double-sampling pseudo-two-path bandpass ΔΣ modulator(Institute of Electrical and Electronics Engineers�(IEEE), 2000-02-01) Shen-Iuan Liu; Chien-Hung Kuo; Ruey-Yuan Tsai; Jingshown WuA double-sampling pseudo-two-path bandpass modulator is proposed. This modulator has an output rate equal to twice the clock rate, uses 2 operational amplifiers (op-amps) for an th-order noise transfer function, and has reduced clock feedthrough in the signal path band. The required clocks can be simpler to implement than the conventional pseudo-two-path techniques. The measured signal-to-noise ratio and dynamic range of the fourth-order double-sampling pseudo-two-path bandpass modulator in a 30-kHz bandwidth at a center frequency of 2.5 MHz (at a clock frequency of 5 MHz) are 62 and 68 dB, respectively.Item A Sub-1V Fourth-Bandpass Delta-Sigma Modulator(Springer Verlag (Germany), 2003-12-01) Hsiang-Hui Chang; Chien-Hung Kuo; Ming-Huang Liu; Shen-Iuan LiuA sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using voltage multipliers or bootstrapping switches. A two-path structure is applied to relax the settling requirement. Implemented in a 0.25-μm one-poly, five-metal standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 58.2 db and a dynamic range (DR) of 64 db in a 60 KHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm2.Item An Ultra Low-Voltage Multibit Delta-Sigma Modulator for Audio-Band Application(2008-05-21) Chien-Hung Kuo; Huai-Juan XieThis paper presents a 0.8 V multibit delta-sigma (DeltaSigma) modulator with a single switched-opamp (SOP) in a 0.18 mum 1P6M CMOS technology. The double-sampling technique is adopted in the modulator to promote the clock efficiency and relax the requirement of SOP. To improve the accuracy of the multibit quantizer in a low-voltage circumstance and reduce the static power, a new switched-capacitor (SC) multibit quantizer without R-string is proposed. The presented DeltaSigma modulator achieves a signal-to-noise-plus-distortion ratio (SNDR) of 88 dB and dynamic range (DR) of 89 dB within a 22 kHz of bandwidth under a 1.25 MHz of clock rate. The power consumption of the presented modulator is 4.2 mW at a 0.8 V of supply voltage.
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