機電工程學系

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系所沿革

為迎合產業機電整合人才之需求,本校於民國 91年成立機電科技研究所,招收碩士班學生;隨後並於民國93年設立大學部,系所整合為「機電科技學系」,更於101學年度起招收博士班學生。103學年度本系更名為「機電工程學系」,本系所之發展方向與目標,係配合國家政策、產業需求與技術發展趨勢而制定。本系規劃專業領域包含「精密機械」及「光機電整合」 為兩大核心領域, 使學生不但學有專精,並具跨領域的知識,期能強化學生之應變能力,以適應多元變化的明日社會。

教學目標主要希望教導學生機電工程相關之基本原理與實務應用的專業知能,並訓練學生如何運用工具進行設計、執行、實作與驗證各項實驗,以培養解決機電工程上各種問題所需要的獨立思考與創新能力。

基於建立系統性的機電工程整合教學與研究目標,本系學士班及研究所之教育目標如下:

一、學士班

1.培育具備理論與實作能力之機電工程人才。

2.培育符合產業需求或教育專業之機電工程人才。

3.培育具備人文素養、專業倫理及終身學習能力之機電工程人才。

二、研究所

1.培育具備機電工程整合實務能力之專業工程師或研發人才。

2.培育機電工程相關研究創新與產業應用之專業工程師或研發人才。

3.培育具備人文素養、專業倫理及終身學習能力之專業工程師或研發人才。

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    Fabrication of nanoporous antireflection surfaces on silicon
    (Elsevier, 2008-11-01) Huang, Mao-Jung; Yang, Chii-Rong; Chiou, Yuang-Cherng; Lee, Rong-Tsong
    After the surface of a silicon wafer has been texturized, the reflectance of the wafer surface can be reduced to increase the power generation efficiency of a silicon-based solar cell. This study presents the integration of self-assembled nanosphere lithography (SANSL) and photo-assisted electrochemical etching (PAECE) to fabricate a nanostructure array with a high aspect ratio on the surface of silicon wafer, to reduce its reflectance. The experimental results show that the etching depth of the fabricated nanopore array structure is about View the MathML source and its diameter is about 90 nm, such that the aspect ratio of the pore can reach about 68:1. The weighted mean reflectance of a blank silicon wafer is 40.2% in the wavelength range of 280–890 nm. Five-minute PAECE without SANSL reduces the weighted mean reflectance to 5.16%. Five-minute PAECE with SANSL reduces the weighted mean reflectance to 1.73%. Further coating of a 200 Å thick silicon nitride layer on the surface of a nanostructure array reduces the weighted mean reflectance even to 0.878%. The novel fabrication technology proposed in this study has the advantage of being low cost, and the fabricated nanostructure array can be employed as an antireflection structure in single crystalline silicon solar cells.